1. Field of the Invention
The present invention relates to a nonvolatile multilevel cell memory, and more particularly, to a technology for performing read operations and write operations with reliability.
2. Description of the Related Art
Nonvolatile semiconductor memories such as a flash memory store data by injecting electrons into the floating gates (or trap gates) of their memory cells to change the threshold voltages of the memory cells. The memory cells rise in threshold voltage when their floating gates contain electrons, and fall when the floating gates contain no electron.
Recently, flash memories that store a plurality of bits in each single memory cell have been developed in order to increase memory capacities.
FIG. 1 shows the distribution of the threshold voltages of memory cells in a four-level NAND type flash memory. The threshold voltages of the respective memory cells fall into any of areas L0, L1, L2, and L3 depending on the data programmed. The areas L0, L1, L2, and L3 correspond to 2-bit data xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d, xe2x80x9c01xe2x80x9d, and xe2x80x9c00xe2x80x9d, respectively. The memory cells of the area L0 have negative threshold voltages and operate as depletion transistors. The memory cells of the areas L1-L3 have positive threshold voltages and operate as enhancement transistors.
Data write (programming) is performed on each memory cell until the threshold voltage exceeds a verification voltage VV (VV1, VV2, VV3). For example, to write logic xe2x80x9c10xe2x80x9d to a memory cell, the programming operation is repeated until the memory cell exceeds the verification voltage VV1 in threshold voltage. Then, the threshold voltages of the respective memory cells are set to any of the areas L0-L3.
Data read is performed by comparing the threshold voltages of the memory cells with reference voltages VR (VR1, VR2, VR3). When a memory cell falls below the reference voltage VR1 in threshold voltage, the data retained in the memory cell is determined to be xe2x80x9c11xe2x80x9d. When a memory cell lies between the reference voltages VR1 and VR2 in threshold voltage, the data retained in the memory cell is determined to be xe2x80x9c10xe2x80x9d. When a memory cell lies between the reference voltages VR2 and VR3 in threshold voltage, the data retained in the memory cell is determined to be xe2x80x9c01xe2x80x9d. When a memory cell exceeds the reference voltage VR3 in threshold voltage, the data retained in the memory cell is determined to be xe2x80x9c00xe2x80x9d.
A reference voltage (conduction voltage) VR4 is supplied to unselected memory cells and selecting transistors to be described later. The reference voltage VR4 is set with a sufficient margin from the area L3.
FIG. 2 shows an overview of a memory cell array of the four-level NAND type flash memory.
The memory cell array comprises a plurality of blocks BLK (BLK0, BLK1, . . . ) and page buffers having sense amplifiers SA. Each block BLK has a plurality of memory cell strings STR. The memory cell strings STR are composed of a plurality of memory cells that are connected in series between selecting transistors. The memory cells have a control gate and a floating gate. Each memory cell is connected at its control gate to a word line WL. The gates of the selecting transistors are each connected to a selecting line SG. Each memory cell string STR is connected at both ends to a bit line BL and a control line ARVSS.
Write operations on the memory cells are performed by supplying a high voltage to word lines WL corresponding to the memory cells to be written and supplying a low voltage to a bit line BL so that electrons are injected to the floating gates of the memory cells through the channels.
Read operations on the memory cells are performed by supplying a reference voltage VR (any of VR1, VR2, and VR3) to word lines WL (for example, WL10 and WL11) corresponding to the memory cells to be read (for example, the circled ones in the diagram), supplying the reference voltage VR4 to the other word lines WL and the selecting lines SG, and supplying a ground voltage to the control line ARVSS. When memory cells to be read exceed the reference voltage VR in threshold voltage, no channel is formed in the memory cells. In this case, no current flows from the bit lines BL to the control line ARVSS. When memory cells to be read fall below the reference voltage VR in threshold voltage, channels are formed in the memory cells and thus currents flow from the bit lines BL to the control line ARVSS. The sense amplifiers SA compare the currents flowing through the bit lines BL with reference currents to determine whether the threshold voltages are higher than the respective reference voltages VR. Then, the logical values of the data stored in the memory cells are determined.
Erase operations on the memory cells are performed by supplying a low voltage to the control gates of the memory cells to be erased and supplying a high voltage to the well regions of the memory cells so as to emit the electrons stored in the floating gates. Here, the control gates of the memory cells not to be erased are rendered floating, for example.
To store multilevel data in a single nonvolatile memory cell, a plurality of reference voltages VR (VR1-VR3) must be each located in between the distributions (L0-L3) of the threshold voltages as shown in FIG. 1. On this account, multilevel memory cells get considerably smaller in read margin as compared to binary memory cells which have a single reference voltage. Consequently, when variations of the semiconductor fabrication process change the write characteristics of the memory cells and shift the distributions L1-L3, insufficient read margins can possibly cause defects.
FIG. 3 shows the distributions of the threshold voltages for situations where the memory cells change in write characteristics. In the diagram, the distributions shown by the broken lines are the normal ones shown in FIG. 1.
For example, if the rates of change of the threshold voltages to write voltages increase due to variations of the fabrication process, the distributions L1-L3 range wider. As a result, a difference between the maximum value in the distribution L1 of the threshold voltages corresponding to logic xe2x80x9c10xe2x80x9d and the reference voltage VR2 (read margin for logic xe2x80x9c10xe2x80x9d) decreases. Similarly, a difference between the maximum value in the distribution L2 of the threshold voltages corresponding to logic xe2x80x9c01xe2x80x9d and the reference voltage VR3 (read margin for logic xe2x80x9c01xe2x80x9d) decreases. In particular, when the distribution L2 ranges wider as shown in the diagram, the read margin for logic xe2x80x9c01xe2x80x9d might practically disappear.
Generally, semiconductor products vary in chip characteristics depending on the positions of the chips on wafers, the positions of the wafers in fabrication lots, and the fabrication lots. For this reason, decreases in read margins can cause a drop in yield. The lower yield in turn can increase the fabrication cost.
It is an object of the present invention to secure operating margins of a nonvolatile multilevel cell memory in order to enhance a fabrication yield.
According to one of the aspects of the nonvolatile multilevel cell memory of the present invention, the cell memory has electrically-rewritable nonvolatile multilevel memory cells. A programming voltage generator generates a plurality of programming voltages to change threshold voltage in each of the memory cells according to logic of write data. A first memory unit stores a plurality of reference values respectively corresponding to a plurality of reference voltages for judging the threshold voltages of the memory cells. At least one of the reference values stored in the first memory unit is rewritable. A reference voltage generator generates the reference voltages, respectively, according to the reference values stored in the first memory unit, when reading data from the memory cells.
Since the reference value(s) for generating the reference voltage(s) is/are rewritable, the reference values can be modified in accordance with the characteristics of the memory cells evaluated in advance. That is, the reference voltages can be changed after the fabrication of the cell memory. Since the reference voltages can be changed in accordance with the characteristics of the memory cells which are dependent on variations of fabrication process, it is possible to improve the read margins of data read from the memory cells. This results in an enhanced fabrication yield.
According to another aspect of the nonvolatile multilevel cell memory of the present invention, the cell memory has electrically-rewritable nonvolatile multilevel memory cells. A programming voltage generator generates a plurality of programming voltages to change threshold voltage in each of the memory cells according to logic of write data. A second memory unit stores a plurality of verification values respectively corresponding to a plurality of verification voltages for verifying distributions of the threshold voltages of the memory cells. At least one of the verification values stored in the second memory unit is rewritable. A verification voltage generator generates the verification voltages, respectively, according to the verification values stored in the second memory unit, when writing data to the memory cells.
Since the verification value(s) for generating the verification voltage(s) is/are rewritable, the verification values can be modified in accordance with the characteristics of the memory cells evaluated in advance. That is, the verification voltages can be changed after the fabrication of the cell memory. Since the verification voltages can be changed in accordance with the characteristics of the memory cells which are dependent on variations of fabrication process, the distributions of the threshold voltages corresponding to the logical values of write data can be optimized in accordance with the write characteristics of the memory cells. As a result, it is possible to improve the read margins of the memory cells with an enhancement in fabrication yield.
According to another aspect of the nonvolatile multilevel cell memory of the present invention, the cell memory has electrically-rewritable nonvolatile multilevel memory cells. A programming voltage generator generates a plurality of programming voltages to change threshold voltage in each of the memory cells according to logic of write data. A programming test circuit operates in a test mode, programs each of the memory cells according to the logic of the write data, and obtains at least one of reference voltages and at least one of verification voltages based on distributions of the threshold voltages of the memory cells programmed.
A reference voltage generator generates a plurality of reference voltages for judging the threshold voltages of the memory cells when reading data from the memory cells. The reference voltage generator generates at least one of the reference voltages according to a value obtained by the programming test circuit. A verification voltage generator generates, when writing data to the memory cells, a plurality of verification voltages for verifying that the threshold voltages of the memory cells exceed a value corresponding to the data. The verification voltage generator generates at least one of the verification voltages according to a value obtained by the programming test circuit.
Consequently, after the fabrication of the cell memory, the programming test circuit can directly evaluate the characteristics of the memory cells and set the reference voltages and the verification voltages within the chip. Since the reference voltages and the verification voltages can be set in accordance with the characteristics of the memory cells which are dependent on variations of fabrication process, it is possible to improve the read margins of data read from the memory cells. In addition, the distributions of the threshold voltages corresponding to the logical values of write data can be optimized in accordance with the write characteristics of the memory cells. This results in an enhanced fabrication yield.
Furthermore, since the programming test circuit built in the cell memory can set the reference voltages and the verification voltages, the test time can be shortened with a reduction in fabrication cost.
According to another aspect of the nonvolatile multilevel cell memory of the present invention, a first memory unit stores a plurality of reference values corresponding to the reference voltages, respectively. At least one of the reference values stored in the first memory unit is rewritable. The reference voltage generator generates the reference voltages according to the reference values stored in the first memory unit.
Since the reference voltage(s) can be set even from the exterior, the characteristics of the memory cells can be evaluated easily, for example, when developing the cell memory or when starting mass production.
According to another aspect of the nonvolatile multilevel cell memory of the present invention, a second memory unit stores a plurality of verification values corresponding to the verification voltages, respectively. At least one of the verification values stored in the second memory unit is rewritable. The verification voltage generator generates the verification voltages according to the verification values stored in the second memory unit.
Since the verification voltage(s) can be set even from the exterior, the characteristics of the memory cells can be evaluated easily, for example, when developing the cell memory or when starting mass production.
According to another aspect of the nonvolatile multilevel cell memory of the present invention, a lowest reference voltage out of the reference voltages and a lowest verification voltage out of the verification voltages are fixed values. The programming test circuit obtains at least one of the reference voltages excluding the lowest reference voltage and obtains at least one of the verification voltages excluding the lowest verification voltage.
Fixing the reference voltage and verification voltage corresponding to memory cell characteristics less susceptible to variations of fabrication process can simplify the logic of the programming test circuit. As a result, the cell memory can be reduced in chip size with a reduction in fabrication cost.
For example, fixing the lowest reference voltage to a ground voltage allows easy generation of this reference voltage.
According to another aspect of the nonvolatile multilevel cell memory of the present invention, the programming test circuit programs the memory cells with the lowest verification voltage, which is a fixed voltage. Next, the programming test circuit measures a highest threshold voltage of a plurality of memory cells programmed, and adds a first margin to the highest threshold voltage measured to obtain one of the reference voltages. Next, the programming test circuit adds a second margin to the obtained reference voltage to obtain next one of the verification voltages. Thereafter, the programming test circuit repeats the foregoing operations to obtain the reference voltages and the verification voltages.
That is, the programming test circuit obtains the subsequent ones of the reference voltages and verification voltages in succession by using the verification voltage that is a fixed voltage. Consequently, by repeating the simple operation flow, it is possible to obtain the reference voltages and the verification voltages in succession. As a result, the programming test circuit can be simplified in logic with a reduction in chip size.
For example, the memory cells each have a floating gate. The first margin is established in accordance with a charge-gain characteristic of increasing in number of electrons in the floating gate. The second margin is established in accordance with a charge-loss characteristic of decreasing in number of electrons in the floating gate.
According to another aspect of the nonvolatile multilevel cell memory of the present invention, a lowest reference voltage out of the reference voltages is a fixed value. The programming test circuit obtains at least one of the reference voltages excluding the lowest reference voltage and at least one of the verification voltages.
Fixing the reference voltage corresponding to memory cell characteristics less susceptible to variations of fabrication process can simplify the logic of the programming test circuit. As a result, the cell memory can be reduced in chip size with a reduction in fabrication cost.
For example, fixing the lowest reference voltage to a ground voltage allows easy generation of this reference voltage.
According to another aspect of the nonvolatile multilevel cell memory of the present invention, the programming test circuit adds a second margin to the lowest reference voltage, which is a fixed voltage, to obtain one of the verification voltages. Next, the programming test circuit measures a highest threshold voltage of a plurality of memory cells programmed with the obtained verification voltage, and adds a first margin to the highest threshold voltage measured to obtain next one of the reference voltages. Next, the programming test circuit adds a second margin to the obtained reference voltage to obtain another one of the verification voltages. Thereafter, the programming test circuit repeats the foregoing operations to obtain the reference voltages and the verification voltages.
That is, the programming test circuit obtains the subsequent ones of the verification voltages and reference voltages in succession by using the reference voltage that is a fixed voltage. Consequently, by repeating the simple operation flow, it is possible to obtain the reference voltages and the verification voltages in succession. As a result, the programming test circuit can be simplified in logic with a reduction in chip size.
For example, the memory cells each have a floating gate. The first margin is established in accordance with a charge-gain characteristic of increasing in the number of electrons in the floating gate. The second margin is established in accordance with a charge-loss characteristic of decreasing in number of electrons in the floating gate.
According to another aspect of the nonvolatile multilevel cell memory of the present invention, a conduction voltage generator generates, when accessing the memory cells, a conduction voltage to be applied to unselected memory cells in memory cell strings by adding a third margin to a maximum value in a highest distribution of threshold voltages out of a plurality of distributions of threshold voltages corresponding to the logic of the write data. The memory cell strings each have a plurality of the memory cells connected in series.
Since the conduction voltage can be changed in accordance with the distributions of the threshold voltages of the memory cells which are dependent on variations of fabrication process, the operating margins of the memory cells can be improved for an enhanced fabrication yield.
According to another aspect of the nonvolatile multilevel cell memory of the present invention, a third memory unit stores the conduction voltage as a conduction value. The conduction value stored in the third memory unit is rewritable. The conduction voltage generator generates, when accessing the memory cell strings each having a plurality of the memory cells connected in series, the conduction voltage to be applied to unselected memory cells in the memory cell strings according to the conduction value stored in the third memory unit. Consequently, the conduction voltage to be applied to unselected memory cells can be changed after the fabrication of the cell memory. Since the conduction voltage can be changed in accordance with the characteristics of the memory cells which are dependent on variations of fabrication process, it is possible to read data from the memory cells with reliability. The improved read margins allow an enhancement in fabrication yield.